Associative computer



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United States Patent O 3,320,594 ASSOCIATIVE COMPUTER Paul M. Davies, Manhattan Beach, Calif., assignor to TRW Inc., a corporation of Ohio Filed Mar. 10, 1964, Ser. No. 350,843 Claims. (Cl. 340-1725) This invention relates to an associative computer and, more particularly, to an organization for a computer that extends the previously known concepts inherent in associative memory systems to the problems of general computation. In my copending applications entitled, Self-Searching Memory," Ser. No. 76,368, now abandoned; Improvement in Self-Searching Memory Systems, Ser. No. 110,098, now Patent No. 3,196,407; Sequential Retrieval Control for a Self-Searching Memory, Ser. No. 151,326, now Patent No. 3,196,409; lmproved Storage Circuits for a Self-Searching Memory, Ser. No. 177,666, now Patent No. 3,210,739; and others, and also copending application entitled Associative Memory System, Ser. No. 272,404 by John L. Rogers and Horace T. Mann, owned by the same assignee, there is shown associative memory systems employing distributed logic techniques that allow simple decisions to be made simultaneously throughout the structure.

In the present invention, more complex distributed logic is provided for simultaneously performing complete programs on sets of data that have been identified by associative structures.

The new technologies of thin films and integrated circuitry have broad implications to computer and memory organization. For instance, the increased simplicity, low power consumption and low cost of active devices permit their more extensive use. At the same time, the problem of interconnecting these devices becomes crucial; for, as the system is made smaller and faster, the problems associated with distributed impedance increase. In addition, there are geometrical constraints such ashe restriction to a plane and the desirability of a lattice-like structure which must be observed.

The associative memory as illustrated in my copending application is a structure which capitalizes upon the potentials of these technologies while complying with the constraints. This is illustrated by the following characteristics:

(l) the structure of the memory is periodic;

(2) memory and computational functions are combined and distributed throughout the entire memory;

(3) logical operation go on simultaneously in all cells of any selected part of the memory; and

(4) records are selected on the basis of content rather than address (although part of the content may be an address).

Perhaps the most crucial characteristic of the associative memory is that it possesses distributed logic which permits simple associations and decisions to be made simultaneously throughout its structure, thus obviating, in some case, the need to search for and withdraw records from the memory one at a time.

Over the past few years studies have also been made of periodic computer structures quite unrelated to the 3,320,594 Patented May 16, 1967 ICC associative memory. The goal here has usually been to spatially relate identical logic modules in an organization capable of performing many computations simultaneously.

This invention is concerned with the concept of combining the principles of the associative memory with the concept of simultaneous computation which employs techniques well known in the art today. The concept of simultaneous computation is achieved by employing a periodically structured computer based upon the associative memory concept for performing any computation on the basis of an internally stored program and performing many such computations simultaneously. It is envisioned that a computer built according to the teachings of this invention would have a computational speed far in excess of presently available computers and, further, that the periodic organization of the associative memory would simplify fabrication and minimize transmission delays. The claimed increase in speed is occasioned by the ability of the associative computer to perform simultaneous computations.

The organization resembles that of the associative memory in that a plurality of memory cells is provided in which each memory cell comprises a control module, a data module, and a tag indicator. The control module comprises means for generating and feeding a tag signal to the tag indicator, in which the tag signal determines the state of the tag indicator and hence establishes what is termed a tagged cell. A writing signal is generated in the control module of each tagged cell and also in the control module of a memory cell immediately adjacent to the tagged cell, each of the data modules having a plurality of positions each individually communicating with corresponding bit positions of an external communieating register. The register is arranged to generate a command signal in each bit position to all memory cells. Each bit position of each data module comprises means responsive to the command signal for generating a nondestruct readout signal indicative of the information stored in said bit position. The nondestruct readout signal in each memory cell is fed to the control module of that cell and also to the control module of an adjacent cell. The nondestruct readout signal generated in an adjacent memory cell is also fed to the control module of the tagged cell. An operand signal generated from an external operand register is fed to the control module of all memory cells for indicating the informational content of said bit. For convenience, the nondestruct readout signals fed to the control module and the external operand signals are called informational input signals. Means in each bit position of the data module of each cell is responsive to a generated writing signal from the control module of that cell and said command signal in that bit position for storing the information contained in the writing signal.

The individual cells are identified by comparing the key portion of the operand register simultaneously with the key portion of the stored data in each memory cell to thereby select the desire-d memory cell.

Cells satisfying the association are tagged and thus selected for further computation.

The control module in each cell contains logic to permit simple logical and arithmetic operations to be performed on an operand stored in the cell and, in the case of binary operations (two operands), on a second operand stored in `an adjacent cell or in an external register.

The sequence of tagging and computing operations performed is controlled by an internally stored program, which itself is withdrawn from the computer, one instruction at a time, by the associating mechanism.

These instructions exert control over the individual cells in which computation is to proceed by means of command coefficients derived from the instruction and transmitted to the control module of each cell.

These control modules each contain certain generalized logic networks whose function is specified in each case by the values of the coefficients received.

The logic performs the specified operations, bit serially, in all tagged cells at once, using the operands specified by certain of the command coefficients.

Further objects and advantages of this invention will be made more apparent by referring now to the accompanying drawings wherein:

FIGURE 1 is a block diagram of an associative computer;

FIGURE 2 illustrates the control unit which supervises the execution of sequential instructions and the acquisition of masks, keys and operands from memory;

FIGURE 3 illustrates a preferred embodiment of a control module;

FIGURE 4 is a diagram of a typical data bit of the memory module; and

FIGURE 5 illustrates a second embodiment of a data bit position.

Referring now to FIGURE l, there is shown a block diagram of an associative computer consisting of a memory block, three registers, M, D and O and a control unit. The memory block consists of n identical cells, each made up of a control module and a data module.

M1-M27 is a mask register which defines the portion of the word in which the association or computation is to be performed. D1 D27 is a communicating register which communicates with the memory cells in reading, tagging (i.e. associating) and computing operations. The M and D registers communicate with the cells of the memory by means of bit lines. Instructions, masks, keys, and operands are read from the memory block into the D register a word at a time in parallel. Instructions are then routed to the control unit, masks to the M register and keys and operands to the O register.

In the performance of any instruction involving a key or an operand, the M register specifies the field of the word to be operated upon. Signals are transmitted along sequential bit lines of the field to all cells. At the same time, sequential bits in the selected eld of the O register are transmitted to all control modules. In tagging operations, these bits from O register are associated with the corresponding bits from the memory modules in all cells of the computer. In one mode of all other binary operations, the bits from the O register enter into the operations performed in the control modules of tagged cells. The second operand comes from the tagged cells themselves. In other modes, the first operand may come from an adjacent cell in memory instead of the O register. The instruction determines the mode. In input operations, the input word enters the O register serially. It is then transmitted serially to tagged control modules and stored in the associated memory modules. In output operations, words are read in fparallel from the memory to the D register; then, they are shifted out serially.

Referring now to FIGURE 2, there is shown a control unit for supervising the execution of sequential instructions and the acquisition of masks, keys and operands from memory. In executing an instruction, it decodes the command and mode portions of the instruction, pro- 4 ducing command coefficients K1-K26 and control signals KILKU" which are transmitted to all control modules.

A unique characteristic of the associative computer is the manner in which these command coefiicients are used in the control modules to perform the desired operation.

Referring now to FIGURE 3, there is shown a block diagram of a typical control module which communicates with the associative memory module by means of three word lines: V1, Si, and Rl. V1 is used to sequentially write ls and Os into selected bits of the ith memory module. Si is used to sequentially transfer selected bits of the ith memory module to the control module where they are being operated upon according to the instruction being performed. R, is a control line which is used to cause the contents of the ith cell to be read out in parallel to the D register.

The control module communicates with adjacent cells by means of SP1, Il l, and Th1 from the cell below and by means of SM1 from the cell above. These lines permit binary operations to be performed upon operands from two adjacent cells and also transfer program command from one cell to the next. This will be explained below.

Finally, the control module receives the command coeii'icients, K1-K26 from the control unit and O from the O register. The latter brings sequential bits of the O register to every control module.

The contr-ol module has two basic tasks. First, when flip-flop, I1, is one, indicating that command resides in the ith cell, it turns on Ri, causing the contents of cell i to be read out to the D register. It then transfers command to cell i+1 by turning on 11+, and turning olir I1. K0, from the control module initiates this operation by which instructions, masks, keys and certain operands, which together constitute the program, are read from memory.

The second task is to perform any of the instructions specified by the command coefficients, K1-K26. This is done by live logical networks, F1, G1, C1 and V1 and Tj. F, is an input network which selects the first operand from among S141, O and SM1. Gi is a generalized sum network which bears a certain resemblance to the network which derives a binary sum from two serially presented operands a'nd a carry input` Ci is a generalized carry network which bears a similar resemblance to the binary carry logic. V1 is an output network which causes the output of G, to be written into cell i under certain circumstances provided the ith cell is tagged, i.e., tag fiip-flop 71:1. (In some cases Vl is controlled by T14.) T, is the network which controls the setting and resetting of the tag flip-flop.

The logic networks shown in FIGURE 3, and which have the properties given by the equations given above, can be constructed by using circuit and logic techniques known to `those skilled in the art.

1 The Boolean equations for these networks are as folows:

where ci and c1' represent the set and reset conditions respectively for C1 and ti and t1 represent the set and reset conditions T1. Gi and C, derive their names from the fact that they reduce to the binary sum and carry equa- 5 tions by setting K6, K7, K9, K12, Kl6 and K17 to l and all other Ks to 0.

A very broad class of functions can be obtained from these formulas, as will be shown below, by selecting appropriate values for the K coefficients. In this sense, the associative computer may be micro-programed. After a specific set of functions has been selected, a number of the coefficients may turn ont to be unused, in which case they may be profitably dropped, thereby simplifying the networks. In the present discussion, we shall assume that all are retained.

Referring now to FIGURE 4, there is shown a logic diagram of a typical data bit of the memory module consisting of the bit storage element itself, Bij, and control gates which relate it to bit lines Wj and OJ and to word lines V1, Si and R1.

To write into memory, one bit of all words is selected by means of line W3. The bit to be written is then transmitted along V1. It may originate in the O register or it may be generated by G1 and C, as the result of a computation. A mechanism associated with the M register generates the W3 signals in sequence throughout the field specified by the mask.

To perform most instructions, including tagging instructions, the Wj lines are used to select the outputs of successive bit elements in every cell. The outputs of the WjBU gates are effectively logically summed over j, although in particular mechanizations no OR gate as such may exist. The resulting signal Sl, is transmitted to the control module where it enters the computation performed by the G1 and C1 networks.

To read a word in parallel from memory to the D register as in the acquisition of instructions, masks, keys and operands, the control module of the appropriate cell pulses R1 causing the BU elements to be read out on the j lines.

In this section, the various types of data stored in the computer will be described and the sequence of operation required to perform a program will be outlined.

TABLE I.-WORD TYPE FORMAIS tion would identify a class of data, the second portion would be reserved for use by sub-routines. In this way, a sub-routine may be used with arbitrary sets of data. The operand portion of the data word is a conventional binary number with sign in bit position 16. Whenever an operand is read from memory, it is transferred to the O register.

(123)=010 identifies an instruction. Instructions consist of a label and a command. The label identifies the first instruction of a routine. A transfer instruction transfers command to this point by associating on the label and turning on the I, ip-fiop. Then, the computer steps along automatically from this point by turning off I1 and turning on IN1 until another transfer instruction is reached. The command is conventional. Instructions remain in the D register. The outputs of the command portion of the D register are decoded by the control unit to produce the command coefiicients.

(l23)=0l1 identifies a mask. The mask is transferred to the M register where it selects data fields for association or computation. A mask bit equal to l means that the corresponding bit position is to be operated upon. Note that (23)=l1 so that the type designation is always a criterion of association.

(l)=l identifies a key. Keys are very similar to date words in that they are transferred to the O register and then, during the performance of an instruction, to the control modules. Keys are in fact the operands used in tagging instructions. The principal distinction of the key is that any of its bits from 2 to 27 may assume any value. The key in conjunction with the mask thus provides considerable freedom in the selection of a class of words. In use, bit 1 is transmitted to the control modules as a zero; bits 2 and 3 may assume any value, so that words of any type except keys may be tagged by association.

A typical program will consist of a sequence of masks, keys, instructions and data words stored in sequential cells of the computer. Control will advance from one of Type l 2 3 4 5 l 7 8 9 1U 11 l? i3 14 l5 Lempty... 000 XXXXXXXXXXXX 2. data word. l] t) l label 3. instruction 0 1 0 label 4.mask 011 (l D 0 O l) l] l) 0 G t) (l D 5.key IXX XXXXXXXXXXXX XXXXXXXXXXX 1111 XXXX operand command Inode l 1 1 1 1 l l X X X X X X X Referring now to Table I, there is shown, for illustration purposes only, an organization of five types of words. Each word is 27 bits long, and the first three bits identify the type. (12302000 indicates that the cell is empty, in which case, the other bits may contain anything. Empty words are not in use and, hence are available for any use.

(1123):()01 indicates a data Word. A data word consists of a label and an operand. The label yis used to identify an operand or a class of operands. Thus, if the same rountine were to be performed on n sets of data, each consisting of, say, three Words, Al, B1 and C1, all the Ais could be identified by the same label; then, a tagging instruction could be used to tag all the As by an equality check on the label field. In practice, the label may be divided into two or more portions.

these cells to the next by means of the I1 Hip-flops. When a particular I, is on, control pulses from the control module caus the zth cell to be read out to the D register. The type of the word is then determined by an examination of bits 1, 2 and 3, `and the appropriate action is taken. If the word is a mask, a key or a data word, the word is transferred to the M or O register. If it is an instruction, the instruction is performed. This may involve the use of the mask to select sequential bits of the field of each word in memory as well as of the O register. It may involve the sequential transmission of the selected field of the O register to the control modules. And, it will involve the transmission of command coefficients and control signals from the control unit to the control modules as well as to other parts The first porof the machine.

TABLE II.-THE

COMMAND LIST Name Meaning I-tag on less I-tag ou equal U-tag on equol I-tag on unequal U-tag on unequal I-tzig on greater Utag on greater U-tag on less Tmnsfer uncoud Transfer ou equal Transfer on unequal Shift left Shift right Shift end around left Shift end around right..

Subtract one. ReverseA subtract Logical product.. Logical sum Clear Clear tags Input Output Turn oi tags where keys mismatch.

Turn on tags where` keys match.

Turn ot tags Whore keys match.

Turn on tags where keys mismatch.

Turn olf tags wherr` stored key is not greater. ITurn on tags where stored key is greater.

Turn ofi tags where stored kry is not less.

Turn ou tags where stored key is less.

Transfer to (445).

Transfer t (4d-i) iflreys match. Transfer to (4-l5) if keys misn'uitch. Shift tagged words luft one bit. Shift tagged words right one bit. End around shift left one bit.

End around shift right one bit. Shift tagged word down one word. Shift tagged word up one word. Interchange tugged Word and neighbor. Shift tag down one word.

Shift tag up one word.

Add Si (tagged) to Fi, result to V.. Add 1 to Si (tagged). result to V.

Subtract Si (tagged) from Fi, result to Vi. Subtract 1 from Si (tagged), result to Vi.

Subtract Fi from Si (tagged), result Vi.

Log. prod. of Si (tagged) and Fi, result` Vi. Log. sum of Si (tagged) and Iii, result to Vf. Clear (123) of Si (tagged).

Turn off all tag flip-flops.

Input one word to tugged cell.

Output one word from tagged cell.

Referring now to Table II, there is shown a list of typical instructions which have been microprogramrned for the associative computer by selecting appropriate values for the command coetiicients. Eight tagging or associating instructions are listed. These are of two types, I and U, which stand for intersection and union associations respectively. In the I type, the tag iiip-tiop is turned olf wherever the association between the transmitted iield (from the O register) and the stored iield fails. Successive applications of I `associations produce intersection sets. In the U type, the tag flip-flop is turned on wherever the association between the transmitted and stored elds suceeds. Successive applications of U associations produce union sets. By means of a series of tagging instructions, an extremely complex set of records `may be identified. For instance, if the memory contains a set of coordinate triplets, X, Y, Z, describing points in space, the computer could select all those points such that X X or X, X X2 and Y Y0 and 2:21.

In addition to the tagging instructions shown, others have been microprogramed including two that find the maximum and minimum values of a specified ticld respectively. These instructions involve certain logical operations not required by the other instructions and so have not been included in the command list. Specifically, the Search for a maximum would proceed as follows:

First, all cells to be tested would be tagged. Next, the most significant bit positions would be selected by the M register and that bit read from all tagged cells simultaneously. It at least one such bit contained a one, a one would be read out. This one would then be sent to all control modules for comparison with the corresponding stored bit. Wherever a mismatch occurred, the tag would be reset. The process would then be repeated for each bit of the field proceeding to the lea-st significant one. At any bit position where a zero was read out, no comparison would be performed. Finally, only the cells containing the maximum would be tagged, and the D register would contain the maximum. The procedure for tagging the minimum is analogous.

Instructions 9 through 11 transfer command to a different routine. It will be recalled that the first instruction of any routine is identified by a characteristic label. The

label of the transfer command is set to the same value. An equality comparison between the two labels causes the Ii iiip-op to be turned on. In the case of TRE and TRU, the transfer is predicated upon a satisfactory association between the stored and transmitted keys.

Instructions 12 through l5 are conventional shift commands which apply of course only to the tagged cells. SHD shifts the selected eld of the tagged words down one cell and SHU shifts them up one cell.

INT causes an interchange of the selected iielcls of all tagged words with their neighbors below. This is a crucial command because it permits non-adjacent words to be brought together. Consider, for instance, a circumstance in which it is desired to perform the same program on a number of sets of data as in a payroll problem. Suppose that each set of data consists of ten words and that it is required to add the second word to the sixth in each set. This would be accomplished by three INT instructions followed by an ADD.

In STD and STU, the tags instead of the data are shifted down or up. This permits a tagging operating to be performed on one word of a set and the tag to be transferred to another.

Instructions 21 through 27 are more or less conventional arithmetic and logical operations. RSB permits an exchange in the selection of minuend and subtrahend.

CLR clears bits 1-3 of all tagged words making the words empty and hence available for new data or programs. CLT clears all tags in memory.

INP causes a word to be read in, transferred via the O-line to all cells and stored in the tagged cells. OUT causes a word to be read from a tagged cell to the D register and then to be shifted out serially.

All of these instructions and many more can be microprogranied using the generalized logic networks described above. In addition, several modes of many of these instructions are available. For instance, in the arithmetic and logical operations involving two operands, one operand comes from the tagged cell; the second may come from the cell above, the cell below or the O-register depending upon the mode. In operations which produce a result, this result may be placed in the tagged cell or the cell below.

TABLE III.-MULT1PLY ROUTINE Type Label Operand or Command Cell Comments D 1 D 0 1 Ai Ai: multiplier 1 0 1 0 Bi Bi: multiplicand 0 1 D 1 1 Ci Cif product 1 0 t) 0 1 CLT Clear tags 1 1 1 1 1 0 0 0 D 0 (l 0 0 t) 0 D 1 Mask for A; digit 0 1 U O 1 1 1 1 1 1 1 l 1 1 1 1 l Key for Ai'S 1 0 'DE U U-tng Ai-'s 1 D STD Shift tags down 1 1 1 1 1 1 1 1 l l 1 1 1 1 Mink 1 i] ADD m=2 Bri-Ci-'Ci 1 i] CLT Clear tags 1 1 1 1 1 Mask 0 1 0 0 1 Key for Ai's 1 0 TE U U-tng At's t) 1 0 1 1 Key for Cis 1 0 TEU U-tag CUS 1 0 SH R Right shift As and C's l 0 CLT Clear tags 1 1 1 l 1 Mask l) 1 1 (l 0 Key for D 1 0 ADO Add 1 t0 l) 1 1 1 1 1 1 1 1 l 1 1 1 1 l l\. sk 1 l) l) t] 1 TRU 1f D-E, transfer to 4 1 o CLR Clear D 0 0l 1 0 1 ll 0 (l 0 0 l) t] D l 1 0 D E312 Referring now to Table III, there is illustrated a program that performs the binary multiplicate of pairs of numbers, A1 and Bi, placing the result in Ci. For each bit of the multiplier A, which is equal to one, B1 is added to C1; then, A1 and C1 are shifted right. After twelve cycles through this loop, the upper half products appear in the Cls. D and E in cells 25 and 26 are used to count the twelve iterations. The routine is entered at cell 4 and eXited at cell 24. Bits 13--15 of the label identify and distinguish A1, B, Ci, D and E for purposes of this subroutine. The remaining bits of the labcl, 4--12, are available to identify the operands by independent categories. Thus, to apply the multiply routine to various sets of data, 13-15 will be left empty. A set of data identied by bits 4-12 will be tagged and appropriate labels Written into bits 13-15. The multiply routine can then be applied.

There are a number of possible variations of the associative computer both in terms of the logical organization and the mechanization. In selecting the model which has been described, we have attempted to choose the simpler and perhaps less sophisticated alternative. For instance, all computation has been performed parallel by word, serially by bit. There are a few operations such as TEI, TEU and INP which can be done parallel by bit.

Referring now to FIGURE 5, there is shown a second implementation of the data bit module implemented by cryogenic techniques. In this implementation key information transmitted from the communicating register is simultaneously compared in the data portion of all memory cells. In the presence of a comparison in any given memory cell, a match indicating signal is generated and fed to the control module of that memory cell. For any given bit position, the information is transmitted along line Wj to all memory cells. The bit position contains the stored information as a circulating current in the path comprising the control element of device 10, line Wj, the control element of device 11, the gate element of device 12, line Wj, and back to the control element of device 10. The path just defined is commonly known as a persistor current path, Well known in the art, and more fully described and claimed in the cited copcnding applications. In the presence of an interrogating comparing signal on ine Wi and depending upon the information being transmitted on line Wj and that stored in the persistent current loop, the gate element of device I1 will become resistive in the presence of a mismatch. The converse is also true in that the gate element of device 11 will remain superconductive in the presence of a match between the stored information and the transmitted key information. In the normal operation, line El is impulsed to thereby cause the gate element of device 13 and the gate element of device 14 to become resistive.

Considering now those bit positions not receiving an enabling pulse on line Ej, it will be observed that element 14 will remain superconducting thereby by-passing the gate element l1. A match indicating signal will appear on line Si [or any given memory cell in the presence of the gate elements on line Si providing a superconductive path. This implies that a match condition must exist for those bit positions that are interrogated resulting in the gate of element 11 being superconductive and that the gate element 14 be superconductive for those bit positions not being interrogated. Should either of these conditions not be present, a resistive element will appear on line Si and no match indicating signal will be generated from that memory cell and a signal indicating that no match occurs will be generated on corresponding 1- line for that memory cell (not illustrated). This system is to be compared with that illustrated in FIGURE 4, in which FIGURE 5 generates a match indicating signal indicative of a complete match of the transmitted key information with the stored information. In FIGURE 4, individual nondestruct bit position readout signals were generated and individually' transmitted to the control module one bit at a time, thereby providing the control module with the information content with the individual bit position. The system of FIGURE 5 can produce the sarne output information as that of. FIGURE 4 by transmitting a binary one on line Wj for a single bit position while simultaneously masking all other bit positions. If the stored information is also a binary one, the output on line Sl will indicate the informational content of the stored bit as a one, whereas an output S will indicate this informational content as a binary 0.

For the writing operation, a command signal from the control module is generated on the Vi line and an enabling signal generated on either EJ or l-fis generated from the mask register depending upon whether information is to be written or not written in that bit position. Having established these conditions prior to writing the information signal to be written is transmitted on line Wj. If information is not to be written into the selected bit position, the enabling pulse on line Ej will cause the gate of element 15 to become resistive thereby by-passing the command writing signal on the Vi line through the gate of element 13. If information is to be stored line E] will be energized thereby causing the gates of elements 13 and 14 to become resisitive. With element 13 resistive the writing command signal on the V, line is caused to flow through the gate of element 15 and the control of element 12, thereby causing the gate of element 12 to become resistive. The informational signal on line W, arrives in the proper time sequence t find element 12 resistive and hence is written in the persistor loop circuit in a well known manner. With this implementation, it is now possible to selectively control individual bit positions and the writing of information into these selected bit positions. Readout is accomplished by generating a signal on the R, line causing element 16 to become resistive and based upon the established convention of causing element to become resistive in the presence of a stored binary one, the resistivity of line 0j will indicate a binary one, whereas a superconductive O,- line will indicate a stored binary 0.

A ladder circuit for selecting the rst of a set of tagged cells is described and claimed in my copending application Serial No. 76,182, entitled Memory Cell Selecting Means, led Dec.16, 1960. Circuits of this type could be combined with the present invention for selecting the rst tagged cell.

A second form of the ladder network has been investigated which requires two tag {lip-flops per control module. If we call these T1 and U1 respectively, the ladder network relates the cells in pairs such that the first member of each pair has Ti=l and the second member has Ulzl. This may be accomplished by transferring current from the left rail to the right rail each time Ti=1 and from the right rail to the left rail whenever U,:1. Current in the rungs is then used to establish the pairing. The same ladder network may be used to transmit information from the T, cells to the associated U, cells. This mechanism makes possible the performance of binary operations on noncontiguous operands and obviates the need for the interchange command.

This completes the description of the embodiments of the invention disclosed and illustrated herein. However, many modifications and advantages will be apparent to persons skilled in the art without departing from the spirit and scope of this invention.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A plurality of memory cells,

each memory cell comprising a control module, a data module and a tag indicator,

said control module comprising means for generating and feeding a tag signal to said tag indicator,

said tag signal determining the state of said tag indicator whereby a memory cell having the tag indicator in a predetermined state being termed a tagged cell,

means in the control module of said tagged cell generating a writing signal,

means in the control module of an immediately adjacent memory cell for generating a writing signal, means in every data module for generating a match indicating signal for determining the existence of a match between stored information in said cell and information from a communicating register, means for feeding the match indicating signal generated in the data module of each memory cell to the control module of that cell,

means for feeding the match indicating signal generated in the data module of said tagged memory cell to the control module of an adjacent cell,

means for feeding the match indicating signal generated in the data module of said adjacent memory cell to the control module of said tagged cell,

means for generating an external operand signal from an operand register from any one bit position to the control modules of all memory cells for indicating the informational content of said bit,

said match indicating signals fed to a control module and said external operand signal being termed information input signals,

logic generating means in each control module responsive to an external function generator control unit for computing the value of at least two logical functions -of said informational input signals,

a rst computed value being used to control the means for generating said tag signal,

a second computed value being used to control the means for generating said writing signal.

said external function generator transmitting the same plurality of control coefficient signals to the logic generating means in each cell for generating identical logical functions,

the computed value of each logical function being independently determined by said informational input signals.

2, A plurality of memory cells,

each memory cell comprising a control module, a

data. module and a tag indicator,

said control module comprising means for generating and feeding a tag signal to said tag indicator,

said tag signal determining the state of said tag indicator whereby a memory cell having the tag indi- Cator in a predetermined state being termed a tagged cell,

means in the control module of said tagged cell for generating a writing signal,

means in the control module of an immediately adjacent memory cell for generating a Writing signal,

means in every data module for generating a match indicating signal, said match indicating signal indicating the existence of a match between stored information in each of said cells and information transmitted to all cells from a communicating register,

means for feeding the match indicating signal generated in the data module of each memory cell to the control module of that cell,

means for feeding the match indicating signal generated in the data module of said tagged memory cell to the control module of an adjacent cell,

means for feeding the match indicating signal generated in the data module of said adjacent memory cell to the control module of said tagged cell,

means for generating and feeding an external operand signal from an operand register from any one bit position to the control modules of all memory cells for indicating the information content of said bit,

said match indicating signals fed to a control module and said external operand signal all being termed informational input signals,

logic means in each control module responsive to an external function generator for computing the value of at least two logical functions of said informational input signals,

a rst computed value being used to control the means for generating said tag signal.

a second computed value being used `to control the means for generating said writing signal,

said external function generator transmitting a plurality of control coeicient signals to the logic means in each cell for generating identical logical functions whereby,

the computed value of each logical function is independently determined by said informational input signals, and

means in each bit position of said communicating register for transmitting a signal having an informational portion and a control portion to all memory cells,

each bit position of each data module having means responsive to said control portion and a writing signal from the associated control module for storing the informational portion of said signal.

3. A plurality of memory cells,

each memory cell comprising a control module, and

a data module,

writing means in the control module of each cell for generating a writing signal,

means in every data module for generating a match indicating signal for determining the existence of a match between stored information in said cell and information from a communicating register,

means for feeding the match indicating signal generated in the data module of each memory cell to the control module of that cell,

means for feeding the match indicating signal generated in the data module to the control module of an adjacent cell,

means within each control module responsive to match indicating signals fed to that control module for controlling said writing means,

each of said data module comprising a plurality of bit positions each individually communicating with a corresponding bit position of said communicating register, and

means in each bit position of said communicating register for transmitting a signal saving an informational portion and a control portion to all memory cells,

each bit position of each data module having means responsive to said control portion and a writing signal from the associated control module for storing the informational portion of said signal.

4. A plurality of memory cells,

each memory cell comprising a control module and a data module, said control module containing a tag indicator,

said control module comprising means for Idetermining the state of said tag indicator whereby a memory cell having the tag indicator in a predetermined state `being termed a tagged cell,

writing means in the control module of each cell for generating a writing signal,

means in the control module of an immediately adjacent memory cell for generating a writing signal,

each of said data modules comprising a plurality of bit positions each individually communicating with corresponding bit positions of a communicating register,

means in each bit position of said communicating register for transmitting a command signal to all memory cells,

each bit position of each data module having means responsive to said command signal for generating a nondestruct readout signal indicative of the informaf tion stored in said bit position,

means for feeding the nondestruct readout signal generated in the data module of each memory cell to the control module of that cell,

means for feeding the nondestruct readout signal generated in the data module to the control module of an adjacent cell,

means for feeding the nondestruct readout generated in the data module of said adjacent memory cell to the control module of said tagged cell,

means for generating an external operand signal from an operand register from any one bit position to the control modules of all memory cells for indicating the informational content of said bit,

said nondestruct readout signals fed to a control module and said external operand signal being termed information input signals,

logic generating means in each control module responsive to an external function generator for computing the value of at least two logical functions of said information-al input signals,

a lrst computed value being used to control the means used to determine the state of said tag indicator,

a second computed value being used to control the means for generating said writing signal, and

said external function generator transmitting the same plurality of control coellicient signals to the logic generating means in each cell for generating identical logical functions,

the computed value of each logical function being independently determined by said informational input signals.

5. A plurality of memory cells,

each memory cell comprising a control module and `a data module, said control module containing a tag indicator,

said control module comprising means for determining the state of said tag indicator whereby a memory cell having the tag indicator in a predetermined state being termed a tagged cell,

writing means in the control module of each cell for generating a writing signal,

means in the control module of an immediately adja- -cent memory cell for generating a writing signal,

each of said data module comprising a plurality of bit positions each individually communicating with corresponding bit positions of a communicating register,

means in each bit position of said communicating register for transmitting a command signal to all memory cells,

each bit position of each data module having means responsive to said command signal for generating a nondestruct readout signal indicative of the information stored in said bit position,

means for feeding the nondestruct readout signal generated in the data module of each memory cell to the control module of that cell,

means for feeding the nondestruct readout signal generated in the data module to the control module of an adjacent cell,

means for feeding the nondestruct readout signal generated in the data module of said adjacent memory cell to the control module of said tagged cell,

means for generating an external operand signal from an operand register from any one bit position to the control modules of all memory cells for indicating the informational content of said bit,

said nondestruct readout signals fed to a control module and said external operand signal `being termed information input signals,

logic generating means in each control module responsive to an external function generator for computing the value of at least two logical functions of said informational input signals,

a first computed value being used to control the means used to determine the state of said tag indicator,

a second computed value being used to control the means for generating said writing signal, and

said external function generator transmitting the same plurality of control coeicient signals to the logic generating means in each cell for generating identical logical functions,

the computed value of each logical function being independently determined by said informational input signals,

and means in each bit position of the data module of each cell responsive to a generated writing signal from the control module of that cell and said command signal in that bit position for storing the information contained in said writing signal.

References Cited by the Examiner UNITED STATES PATENTS l/l966 Seeber et al 340-1725 3/1966 Davies S40-172.5 

3. A PLURALITY OF MEMORY CELLS, EACH MEMORY CELL COMPRISING A CONTROL MODULE, AND A DATA MODULE, WRITING MEANS IN THE CONTROL MODULE OF EACH CELL FOR GENERATING A WRITING SIGNAL, MEANS IN EVERY DATA MODULE FOR GENERATING A MATCH INDICATING SIGNAL FOR DETERMINING THE EXISTENCE OF A MATCH BETWEEN STORED INFORMATION IN SAID CELL AND INFORMATION FROM A COMMUNICATING REGISTER, MEANS FOR FEEDING THE MATCH INDICATING SIGNAL GENERATED IN THE DATA MODULE OF EACH MEMORY CELL TO THE CONTROL MODULE OF THAT CELL, MEANS FOR FEEDING THE MATCH INDICATING SIGNAL GENERATED IN THE DATA MODULE TO THE CONTROL MODULE OF AN ADJACENT CELL, MEANS WITHIN EACH CONTROL MODULE RESPONSIVE TO MATCH INDICATING SIGNALS FED TO THAT CONTROL MODULE FOR CONTROLLING SAID WRITING MEANS, EACH OF SAID DATA MODULE COMPRISING A PLURALITY OF BIT POSITIONS EACH INDIVIDUALLY COMMUNICATING WITH A CORRESPONDING BIT POSITION OF SAID COMMUNICATING REGISTER, AND 